SHA-3 Hash Crypto Engine

The SHA3-B219 is a crypto IP Core for hardware offloading of Hash algorithms in FPGA, SoC, and ASIC technologies.

The engine implements the Secure Hash Algorithm 3 (SHA‑3) family according to FIPS 202 standard. It includes fixed-length (SHA3-224, SHA3-256, SHA3-384, SHA3‑512) and extendable-output functions (SHAKE128, SHAKE256). It also supports the KMAC (Keccak Message Authentication Code) operation according to NIST 800-185.

SHA3-B219 implements the Keccak sponge construction, including the insertion of the domain separation suffix, message padding, and data permutation functions.

With the context switching functionality, the internal state of the Keccak engine can be saved and restored as needed to process other data.

Portable to any Xilinx, Intel, or Microsemi device, the IP Core is compliant with FIPS 140-3 and provides the highest performance in a minimum area.

SHA3‑B219 includes AMBA AXI interfaces and a register map with user-programmable parameters to select the Hash function, the length of the XOFs digest, and the KMAC configuration. ANSI C drivers are provided for a fast integration into the target platform.

SHA-3 Hash Crypto Engine

SHA-3 Operations

Function

Performance, Gbps

@300 MHz

SHA3-224 14.4
SHA3-256 13.6
SHA3-384 10.4
SHA3-512 7.2
SHAKE128, KMAC128 15.5
SHAKE128, KMAC128 13.6

Resources

Device Family

LUT

Register

Xilinx Spartan-7, Artix-7, Kintex-7, Virtex-7 4.8K 4.2K
Kintex/Virtex Ultrascale 4.8K 4.2K
Artix/Kintex/Virtex Ultrascale+ 4.8K 4.2K
Versal ACAP 4.6K 4.2K
Intel MAX 10 / Cyclone 10 LP 7.9K 4.2K
Cyclone V 5.0K 4.2K
Arria 10 5.0K 4.2K
Stratix V 5.0K 4.2K
SHA-3 Functions

The SHA3-B219 IP Core implements the following cryptographic algorithms specified in the FIPS 202 and NIST 800-185 standards:

    •  Fixed-Length Hash Functions
      • SHA3-224
      • SHA3-256
      • SHA3-384
      • SHA3-512
    •  Extendable-Output Functions (XOFs)
      • SHAKE128
      • SHAKE256
    •  Keyed Hash Functions
      • KMAC128
      • KMAC256

Based on the Keccak algorithm, the IP Core implements the sponge construction of the SHA-3 standard, which includes the insertion of the domain separation suffix, padding of the input string, and permutation using the Keccakp mathematical function.

Interfaces

The IP Core includes three 64-bit AXI4-Stream interfaces for high-speed transfer of the input message, the KMAC key, and the output hash value. The AXI4-Lite interface provides access to the register map for selecting the SHA-3 function, the length of the SHAKE digest, and the KMAC parameters.

Licensing

The IP Core is provided as encrypted netlist for one device family, under a perpetual Site Licence. It includes 12 months of maintenance and remote support for the integration of the module in your platform.

Deliverables
  • Targeted, timing closed Netlist
  • Design Constraints
  • Simulation Model
  • User Manual
  • ANSI C drivers
Downloads
Ordering
Features
  • Cryptographic Hashing
    • SHA3-224
    • SHA3-256
    • SHA3-384
    • SHA3-512
  • Extendable-Output Functions
    • SHAKE128
    • SHAKE256
  •  KMAC Support
  •  Context Switching
  •  FIPS 202, FIPS 140-3 Compliant
  •  Portable to any FPGA or ASIC
  •  AMBA AXI Interfaces
Applications
  •  Digital Signature
  •  Encrypted Data Storage
  •  User Authentication
  •  Secure Communications
  •  Post-Quantum Cryptography
References
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