True Random Number Generators (TRNG)

Our TRNG IP cores generate reliable physical true random sequences for any FPGA, SoC, or ASIC design targeting cryptographic applications. The non-deterministic entropy source is based on multi-phase oscillators, producing a high‑quality RNG.

The IP Cores are compliant with NIST 800‑90B, FIPS 140-3, and AIS‑31 PTG.2 standards.

TRNG-P200 implements simultaneous raw and post-processed outputs and includes a comprehensive set of statistical tests according to NIST 800-22. It is a qualified product by the National Cryptologic Center (CCN).

TRNG-P201 is optimised for low resource utilisation, while keeping the statistical performance and the compliance with NIST and BSI standards.

Portable to any AMD (Xilinx), Intel (Altera), or Microchip (Microsemi) device, both IP cores pass NIST 800-22, AIS-31, and Diehard test suites. Operation is continuously monitored, triggering alarms when fault conditions are detected.

The IP cores include AMBA-AXI interfaces and a register map with user-programmable parameters to configure the random sequence rate, post-processed outputs, health tests, and alarms management.

TRNG IP Cores Comparison

TRNG-P200 TRNG-P201
Typical Resource Utilisation LUT 5K 2.5K
Register 5K 2.3K
NIST Health Tests Repetition Count
Adaptive Proportion
Frequency (Monobit)
Runs
Frequency within a Block
Longest-Run-of-Ones in a Block
Overlapping Template Matching
Cumulative Sums
NIST Tests Execution Mode Continuous
Triggered
Regular Intervals
Entropy Source Tests
Known-Answer Tests (KAT)
Output Sequences Raw
Parity Filter (2-bit)
Configurable Parity Filter
Configurable Polynomial Encoder
Simultaneous Raw and Post-processed Outputs

TRNG-P200

Device Family

LUT

Register

Output Rate (SP)

AMD Xilinx Spartan-7, Artix-7 (*) 4.7K 5.0K

212 Mbps (1)
270 Mbps (2)

Kintex-7, Virtex-7 (*) 4.7K 5.0K

320 Mbps (1)
405 Mbps (2)

Kintex/Virtex Ultrascale 4.6K 5.0K

415 Mbps (1)
461 Mbps (2)

Artix/Kintex/Virtex Ultrascale+ (*) 4.7K 5.0K 575 Mbps (1)
Versal ACAP 4.3K 5.0K 575 Mbps (1)
Intel MAX 10, Cyclone 10 LP 7.6K 4.5K 130 Mbps (7)
Cyclone V 5.3K 4.8K 211 Mbps (7)
241 Mbps (6)
Arria 10 5.4K 4.7K

300 Mbps (3)
373 Mbps (2)

Stratix V 5.5K 4.7K 486 Mbps (1)

TRNG-P201

Device Family

LUT

Register

Output Rate (SP)

AMD Xilinx Spartan-7, Artix-7 (*) 2.5K 2.3K

212 Mbps (1)
270 Mbps (2)

Kintex-7, Virtex-7 (*) 2.5K 2.3K

320 Mbps (1)
405 Mbps (2)

Kintex/Virtex Ultrascale 2.5K 2.3K

415 Mbps (1)
461 Mbps (2)

Artix/Kintex/Virtex Ultrascale+ (*) 2.5K 2.3K 575 Mbps (1)
Versal ACAP 2.2K 2.3K 575 Mbps (1)
Intel MAX 10, Cyclone 10 LP 4.1K 1.7K 130 Mbps (7)
Cyclone V 2.7K 1.9K 211 Mbps (7)
241 Mbps (6)
Arria 10 2.7K 1.8K

300 Mbps (3)
373 Mbps (2)

Stratix V 2.8K 1.8K 486 Mbps (1)
 

(*) Also applicable to Zynq SoC
(SP) Speed Grade

Entropy Source

The non-deterministic entropy source is sampled at the input clock frequency to generate true random bits. The maximum rate of the raw random sequence depends on the target device. The raw output is post-processed using parity filters, and a configurable polynomial encoder with predefined BCH codes.

Interfaces & Register Map

The TRNG provides raw and post-processing output sequences through AXI4-Stream interfaces. The core includes a register map with a complete set of user-programmable parameters to configure the polynomial encoder, output rate, health tests thresholds, and alarms behaviour. Access to registers is implemented using an AXI4-Lite interface.

Health Tests

The TRNG IP Cores include the following configurable health tests:

    • Total failure of the Entropy Source and Known-Answer tests according to AIS-31.
    • Repetition Count and Adaptative Proportion according to NIST 800‑90B.
    • Monobit and Runs test according to NIST 800‑22.
    • Frequency Test within a Block, Longest Run of Ones in a Block, Overlapping Template Matching, and Cumulative Sums according to NIST 800‑22 (TRNG-P200 only)

Health tests trigger alarms when fault conditions are detected. It is possible to specify which critical warnings disable the output data.

Licensing

Each IP Core is provided as encrypted netlist for one device family, under a perpetual Site Licence. It includes 12 months of maintenance and remote support for the integration of the TRNG core in your platform.

Deliverables
  • Targeted, timing closed Netlist
  • Design Constraints and Scripts
  • User Manual
  • ANSI C drivers for registers configuration
Downloads
Video Demo
Ordering
Features
  •  High-quality Entropy Source
  •  AIS-31 PTG.2 Compliant
  •  FIPS 140-3 Compliant
  •  NIST 800-90B Health Tests
  •  Passes NIST SP800-22 Test Suite
  •  Passes Diehard Battery of Tests
  •  Internal Fault Detection
  •  Portable to any FPGA or ASIC
  •  AMBA-AXI Interface
Applications
  •  Secure Communications
  •  Encrypted Data Storage
  •  Cryptographic Protocols
  •  Electronic Transactions
  •  Noise Generation
References
ENS Qualified Product
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